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Preliminary Data Sheet
Rev.0.9
20.09.2011
DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS
(0°C ≤ T CASE ≤ + 85°C; V DDQ = +1.5V ± 0.075V, V DD = +1.5V ± 0.075V)
AC CHARACTERISTICS
10600-999
8500-777
PARAMETER
SYMBOL
MIN
MAX
Min
MAX
Unit
Clock cycle time
CL = 10
t CK (10)
1.5
<1.875
-
-
ns
CL = 9
CL = 8
CL = 7
CL = 6
CK high-level width
CK low-level width
Data-out high-impedance
t CK (9)
t CK (8)
t CK (7)
t CK (6)
t CH (avg)
t CL (avg)
t HZ
1.5
1.875
1.875
2.5
0.47
0.47
<1.875
<2.5
<2.5
3.3
0.53
0.53
250
-
-
1.875
2.5
0.47
0.47
-
-
<2.5
3.3
0.53
0.53
300
ns
ns
ns
ns
t CK
t CK
ps
window from CK/CK#
Data-out low-impedance window
t LZ
-500
250
-600
300
ps
from CK/CK#
DQ and DM input setup time
t DS(Base)
30
25
ps
relative to DQS
DQ and DM input hold time
t DH(Base)
65
100
ps
relative to DQS
DQ and DM input setup time
t DS1V
180
200
ps
relative to DQS V REF =1V/ns
DQ and DM input hold time
t DH1V
165
200
ps
relative to DQS V REF =1V/ns
DQ and DM input pulse width
t DIPW
400
490
ps
( for each input )
DQS, DQS# to DQ skew, per
t DQSQ
125
150
ps
access
DQ-DQS hold, DQS to first DQ
t QH
0.38
0.38
t CK
to go non-valid, per access
(AVG)
DQS input high pulse width
DQS input low pulse width
DQS, DQS# rising to/from CK,
t DQSH
t DQSL
t DQSCK
0.45
0.45
-255
0.55
0.55
255
0.45
0.45
-300
0.55
0.55
300
t CK
t CK
ps
CK#
DQS, DQS# rising to/from CK,
t DQSCK
1
10
1
10
ns
CK# when DLL disabled
DLL_DIS
DQS falling edge to CK rising
t DSS
0.2
0.2
t CK
- setup time
DQS falling edge from CK rising
t DSH
0.2
0.2
t CK
- hold time
DQS read preamble
DQS read postamble
DQS write preamble
DQS write postamble
Positive DQS latching edge to
t RPRE
t RPST
t WPRE
t WPST
t DQSS
0.9
0.3
0.9
0.3
- 0.25
Note1
Note2
+ 0.25
0.9
0.3
0.9
0.3
- 0.25
Note1
Note2
+ 0.25
t CK
t CK
t CK
t CK
t CK
associated clock edge
Address and control input pulse
t IPW
620
780
ps
width ( for each input )
CTRL, CMD, Addr setup to CK,
t IS(Base)
65
125
ps
CK#
CTRL, CMD, Addr setup to CK,
t IS(1V)
240
300
ps
CK#
1
2
V REF @ 1V/ns
The maximum preamble is bound by t LZDQS (MAX)
The maximum postamble is bound by t HZDQS (MAX)
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
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